As the minimum feature size of semiconductor devices continues to decrease, the supply voltage for circuits is also decreased. One approach to maintain high circuit performance with such low operating supply voltages is to lower the threshold voltage (VT) of transistors to increase the corresponding drive current. However, as VT becomes lower, the leakage current of the transistor in the ‘off’ condition increases rapidly. This results in an undesirable increase in power supply drain current for circuits both in the quiescent and in the active states. This ‘off’ leakage current becomes an important issue especially in large-scale integration (LSI) devices employed in portable equipment whose battery life is affected significantly by the unwanted leakage current.
To reduce the leakage current during the quiescent state, several circuit configurations have been proposed using switch transistors to break open leakage paths. One of the conventional switching approaches is illustrated in FIG. 1. This approach is often referred to as multi-threshold (MT) CMOS approach. In this circuit, a PMOS switch transistor 100 is inserted between the power supply (VDD) 101 and the virtual power supply (VVDD) 102. The switch transistor 100 has higher threshold voltage, VT=HVT, than transistors in the functional circuit 103, which have a low threshold voltage, VT=(LVT). The switch 100 is turned ‘on’ while the circuit is ‘active’, and it is turned ‘off’ when the circuit is in the quiescent or ‘sleep’ mode, this control being provided by control signal 104. The leakage current during the ‘sleep’ mode is significantly reduced compared with the ordinary LVT circuits not using the HVT switch transistor 100.
Another conventional approach to quiescent current reduction is often referred to as ‘super cut-off’ (SC) CMOS. This approach uses a single threshold voltage LVT technology and is illustrated in FIG. 2. Since the switch transistor 200 is fabricated by the same LVT technology as transistors of the functional circuit 203, the ‘super cut-off’ approach allows for lower fabrication cost than multi-threshold MT CMOS. The gate of the switch transistor 200 is pulled up by control signal 204 beyond the supply voltage by an amount sufficient to strongly cut the leakage current of the LVT switch transistor 200 in the ‘sleep’ mode.
However, in such conventional switching approaches, data retention of memory circuits, such as latches and flip-flops, is a serious concern. The circuit diagram of the conventional single-step (SS) latch is illustrated in FIG. 3A. The clock driver circuit illustrated in FIG. 3B. Data is input at 301. Functional clock FC 302 is derived from the clock driver of FIG. 3B, which is driven by narrow-width clock pulses 304 from a special pulse generation circuit. When FC 302 goes to the ‘high’ state, data is stored in the latch 305 comprised of cross-coupled clocked inverters 306 and 307. The latched data appears at Q 308 after FC goes ‘high’, delayed only by the gate delay of inverter 310. Scan data SD 309 and test clock TC 310 operate in similar manner with D 301 and FC 302 as inputs, respectively. The SD inputs and TC inputs are used only in the scan test mode.
The circuit diagram of a single step latch with switch transistor for sleep mode control is illustrated in FIG. 4. Switch transistor 400 performs the connection or disconnect of virtual power supply 401 and physical power supply 409 under the control of input 404. In this circuit, the data latched in latch 405 is not retained over the sleep mode because the circuit is separated from the power supply by switch transistor 400 during the sleep mode and the stored charge, on nodes 411 and 412, for example, will be lost.
FIG. 5 illustrates another approach of applying he switch-transistor scheme to a single step latch. In this circuit the key latch circuit elements 506 and 507 for data retention are clocked inverters and are connected to the power supply directly so that they are kept active during the ‘sleep’ mode. However, in this circuit configuration the ‘off’ leakage current is of concern again because of the leakage paths denoted by arrows labeled 509, 510, 511, and 512. One approach to reduce leakage is to use HVT transistors in these leakage paths. This would require larger geometry transistors because WIT transistors have less drive current than LVT transistors. Furthermore, such multi-threshold technology combining both LVT and HVT transistors requires higher fabrication cost than a single threshold technology.